1. Field of the Invention
The present invention generally relates to a built-in self repair (BISR) technique of a memory, in particular, to a built-in redundancy analyzer (BIRA) and a redundancy analysis method thereof.
2. Description of Related Art
It may be a big problem for testing a chip when the circuit on the chip includes a plurality of memories. The input and output terminals of all the memories have to be connected to outside of the chip if an external apparatus is used for testing the chip. Such a large quantity of wirings takes up a lot of chip space and increases the complexity of the circuit layout, and moreover, is not realistic when the pin number of the chip is limited. Accordingly, a concept of built-in self test (BIST) is provided. BIST is to build a testing circuit and the memories to be tested on the same chip, so that the input and output terminals of the memories do not have to be connected to outside of the chip for testing purpose. After repairable memory is invented, BIST technique has been extended to built-in self repair (BISR) technique.
FIG. 1 illustrates a conventional BISR circuit. Referring to FIG. 1, a built-in tester 102 is used for testing a repairable memory 101. If a fault occurs, the built-in tester 102 notifies the fault location to a built-in redundancy analyzer (BIRA) 103. The BIRA103 then analyzes the fault information and issues an optimal repair method to the repairable memory 101. The repairable memory 101 repairs the column or row containing the fault by using a built-in redundancy, namely, a redundancy column and/or a redundancy row, according to this repair method.
The conventional BIRA can only analyze the fault information of a single memory and is designed based on the parameter of this memory. The aforementioned parameter includes the length of column address, the length of row address, the length of word, the number of redundancy column, and the number of redundancy row of the memory, wherein length refers to bit number. Multiple built-in redundancy analyzers are required correspondingly if the circuit on a chip includes a plurality of memories, which not only takes up a lot of chip space but also increases the cost of the chip. The circuit illustrated in FIG. 1 becomes unrealistic when the number of built-in redundancy analyzers increases along with the increase of the number of memories.
FIG. 2 illustrates another conventional BISR circuit, wherein the built-in tester 102 and the BIRA 103 illustrated in FIG. 1 are replaced by a processor 204, and the testing and repair analysis are both completed by a software in the processor 204. Since the software can adjust itself based on the parameters of different memories, the processor 204 can be used for testing and analyzing multiple repairable memories 201˜203. However, the processor takes longer time for testing and analyzing the memories and takes up more chip space when compared with the circuit illustrated in FIG. 1.
As described above, an ideal BISR circuit is desired for a chip having a plurality of memories.